|
週次 |
日期 |
單元主題 |
|
第1週 |
02/16 |
Introduction |
|
第2週 |
02/23 |
Logic Circuits and Writing Verilog |
|
第3週 |
03/02 |
Logic Circuits and Writing Verilog (II) |
|
第4週 |
03/09 |
Implementation Technology |
|
第5週 |
03/16 |
Using Quartus II and DE2 + Optimized Implementation |
|
第6週 |
03/23 |
Optimized Implementation, Number Representation |
|
第7週 |
03/30 |
Modular Combinational Logic |
|
第8週 |
04/06 |
Number Systems and Codes |
|
第9週 |
04/13 |
Combinational Circuit Design with Programmable Logic Devices |
|
第10週 |
04/20 |
Combinational-circuit Building Blocks |
|
第11週 |
04/27 |
Introduction to Sequential Devices |
|
第12週 |
05/04 |
Midterm |
|
第13週 |
05/11 |
Modular Sequential Logic |
|
第14週 |
05/18 |
5/18當天停課, 改成(5/16)參加賽前說明會 (台大電機系博理館)
Analysis and Synthesis of Synchronous Sequential Circuits |
|
第15週 |
05/25 |
Simplification of Sequential Circuits (project proposal) |
|
第16週 |
06/01 |
Sequential Circuits with Programmable Logic Devices |
|
第17週 |
06/08 |
Final project demo |
|
第18週 |
06/15 |
Final (Verilog coding) 2:20pm開始,
不能上機! |